High Throughput N-Modular Redundancy for Error Correction Design of Memristive Stateful Logic

Abstract Memristive stateful logic is one of the most promising candidates to implement an in-memory computing system that computes within the storage unit. It can eliminate the costs for the data movement in the traditional von Neumann system. However, the instability in the memristors is inevitable due to the limitation of the current fabrication technology, which incurs a great challenge for the reliability of the memristive stateful logic. In this paper, the implication of device instability on the reliability of the logic event is simulated. The mathematical relationship between logic reliability and redundancy has been deduced. By combining the mathematical relationship with the vector-matrix multiplication in a memristive crossbar array, the logic error correction scheme with high throughput has been proposed. Moreover, a universal design paradigm has been put forward for complex logic. And the circuit schematic and the flow of the scheme have been raised. Finally, A 1-bit full adder (FA) based on the NOR logic and NOT logic is simulated and the mathematical evaluation is performed. It demonstrates the scheme can improve the reliability of the logic significantly. And compared with other four error corrections, the scheme which can be suitable for all kinds of R-R logics and V-R logics has the best universality and throughput. Compared with the other two approaches which also need additional CMOS circuits, it needs fewer transistors and cycles for the error correction.