Curvilinear mask solutions for full-chip EUV lithography

The application of curvilinear masks for DUV lithography has demonstrated benefits over Manhattan masks for improved process window, mask consistency, sidelobe printing control and MRC. However, the prior high cost of using curvilinear masks has limited the usage to critical areas and prevented its broader adoption in production. With recent technology advancements, multi-beam mask writers are capable of meeting specifications of advanced patterning nodes, and curvilinear masks can now be extended to advanced EUV lithography generations. ILT is known for its advantage of creating a patterning-optimized curvilinear mask through field operations. It has been used to solve the most challenging lithography problems with superior quality. Computational costs have previously limited widespread ILT deployment to only the most advanced production mask synthesis flows. To create curvilinear masks for full-chip layout, a faster curvilinear OPC solution for less critical regions will be a valuable complimentary option to curvilinear ILT. In this paper, we will present a hybrid curvilinear mask solution with ILT and Curve OPC for full-chip EUV layers. Results of full-chip EUV in lithographic performance and runtime will be compared among different solutions including traditional Manhattan OPC, Curvilinear ILT and hybrid machine learning (ML) ILT plus Curve OPC. Another important factor of curvilinear mask advancement is data volume. We will present our Curve OPC solution with Cubic Bezier curve to control the data volume of curvilinear masks. The mask write process is playing an increasingly important role in overall manufacturing flow. Therefore, we also present an extended mask synthesis flow utilizing a mask error correction (MEC) solution for curvilinear masks written by a multi- beam writer.