Synthesizing Legacy String Code for FPGAs Using Bounded Automata Learning

The adoption of hardware accelerators, such as field-programmable gate arrays, into general-purpose computation pipelines continues to expand, but programming models for these devices lag far behind their central processing unit (CPU) counterparts. While high-level synthesis (HLS) can help port some legacy software, many programs perform poorly without manual, architecture-specific optimization. We propose an end-to-end approach combining dynamic and static analyses to learn a model of functional behavior for off-the-shelf legacy code and synthesize a hardware description from this model. Our prototype implementation can correctly learn functionality for string kernels that recognize regular languages and provides a near approximation otherwise. We evaluate our prototype tool on a benchmark suite of real world, legacy string functions mined from GitHub and successfully synthesize—without modification or annotation—over 80% (72% exactly and a further 11% approximately). Traditional HLS, only after extensive modification and custom testbench generation, can synthesize the same number of benchmarks, but with results that have higher hardware requirements and lower maximum clock rates.