Equivalent thermal model of through silicon via and bump for advanced packaging of integrated circuits

Thermal issue is a quite critical factor in influencing the performance of integrated circuits (ICs) with the increase of the device integration density. Through silicon via (TSV) and bump have large significance in temperature analysis and thermal-aware physical optimizations in 2.5-D or 3-D ICs. In this paper, a new equivalent thermal model of TSVs and bumps is proposed to capture the anisotropic characteristics of the thermal conductivities of complicated structures and alleviate the computational expenses required for large-scale 3-D stacked chips or 2.5-D chiplet heterogeneous integration (CHI). The present equivalent model not only investigates the vertical direction conductivities of TSVs with insulating layer and bumps without insulating layer, but also incorporates the heat transfer effects of lateral direction in consideration of geometrical parameters. The equivalent method has been further extended to construct an equivalent thermal model of TSV and bump arrays to consider the anisotropic effects of thermal conductivities. The proposed model has been verified by comparing the calculated thermal conductivities with the results of finite element analysis (FEA). It is found that the simulation error of the present model is <2 % compared with the calculated FEA results. Furthermore, the influences of the design structures of TSVs and bumps on the thermal conductivities are also performed to validate the accuracy of the equivalent model and describe the primary factor impacting the thermal behavior of a 2.5-D or 3-D chip. Therefore, the consistency of the equivalent thermal model with FEA simulation indicates that the proposed equivalent TSV and bump model can be easily integrated into a thermal analysis framework to construct a more efficient thermal simulation tool to improve the accuracy of temperature distribution for CHI or 3-D ICs.