Low‐Power Logic‐in‐Memory Complementary Inverter Based on p‐WSe ₂ and n‐WS ₂

Abstract Transition metal dichalcogenides have been considered as candidate materials to construct logic‐in‐memory devices for realizing non‐von‐Neumann architecture. Thus, reducing the power consumption is extremely critical for their applications in big data and artificial intelligence. Here, a low‐power logic‐in‐memory device is demonstrated by constructing complementary inverter with p‐WSe 2 and n‐WS 2 transistors. By engineering the interface states between WSe 2 (WS 2 ) and substrate artificially, non‐volatile memory with resistance ratio of 10 4 and 10 3 after 500 s are achieved in individual WSe 2 and WS 2 transistors, respectively. Furthermore, a complementary inverter with a retention time longer than 500 s is realized by connecting p‐WSe 2 and n‐WS 2 transistors. More importantly, the static operating source‐drain current I ds of this inverter is around 0.5/0.1 nA at low/high resistance states with source‐drain voltage V ds = 5 V, and the hysteresis window is located around 0 V, both of which can reduce the energy consumption dramatically and leads to the low operation power. This work provides a convenient strategy to build a non‐von‐Neumann device toward post‐Moore information processing technology.