A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques

Kazunori Hasebe,Shinichirou Etou, Daisuke Miyazaki, Taiki Iguchi, Yuki Yagishita, Mika Takasaki, Takeru Nogamida, Hiroyuki Watanabe,Tomohiro Matsumoto,Yasushi Katayama

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）

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摘要

Noise-Shaping (NS) SAR ADCs can have high Dynamic Range (DR) and be easily adopted to IoT, audio and many other applications. This paper proposes four techniques to improve the DR and conversion speed of NS SAR ADCs. A prototype NS SAR ADC achieves SNDR/SNR/SFDR of 98.3dB/99.3dB/108.5dB with 100kHz bandwidth and 12.8MS/s. Schreier FoM reaches 175.3dB.

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关键词

noise-shaping SAR ADC,mismatch error shaping,data weighted averaging,asynchronous clock,redundancy bit

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