Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) Operation

Nachiket Desai,Harish K. Krishnamurthy,Suhwan Kim,Christopher Schaef,Sheldon Weng,Beomseok Choi,William J. Lambert,Krishnan Ravichandran,James W. Tschanz,Vivek De

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）

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摘要

A 10-tile buck IVR using 0.9nH-1.4nH 3D-TSV-based package-embedded inductors demonstrates up to 37.6% higher efficiency than LDO. Communication-free inter-tile ganging is achieved with flat efficiency over a 10mA-1A load range. Stability-aware interleaving of IVR tiles in DCM shows up to 34% reduction in output ripple compared to zero interleaving.

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关键词

CMOS active silicon interposer,IVR tiles,communication-free inter-tile ganging,10-tile buck IVR,digitally controlled ON-time discontinuous conduction mode,heterogeneous 3D-TSV-stacked system-in-package,package-embedded inductors,fully integrated voltage regulators,size 22.0 nm,current 10 mA to 1 A

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