Complexity Reduced IIR Filter Design for FPGA

In this paper, a method of high order IIR filter design is proposed in which the coefficients in the canonical binary number system representation are searched by the simulated annealing algorithm. The high-quality IIR filters are designed using the all-pass filter stages, methods of masking filters and multiplied delays. It was proven, that if the coefficients of the multiplierless filter have no more than three summands in their representation, then its pipelined implementation in FPGA has the highest clock frequency. The use of the VHDL language in all the steps of the filter design helps to speed-up and improve the filter optimization.