Study of gate current in advanced MOS architectures

We have carried out a comprehensive study of the gate current (IG) in advanced MOS architectures for different gate lengths and cross-section areas using an in–house simulation tool. We have considered only direct tunneling under the assumption that trap concentration and therefore the trap assisted current would be small in a matured technology. We have also studied the impact of the interfacial (IL) SiO2 layer on the gate current in the high-κ gate stack. Our results suggest that IL leads to an increase in the gate current for equivalent EOT. They also highlight that reduction in the cross-section area leads to a significant increase in the IG.