A generalized sub-circuit model to enable accurate CHC aging simulation and spatial defect profiling in LDMOS

This work demonstrates a novel sub-circuit based model to capture the unique bias dependence of Channel-Hot-Carrier (CHC) induced on-resistance (RDSon) degradation in Laterally Diffused MOSFET (LDMOS). The proposed methodology also provides a simple and fast metrology to identify spatial location of CHC induced defect generation in LDMOS. SPICE simulations of a half bridge converter circuit using the new proposed model show significant differences in key performance metrics compared to a conventional model demonstrating the importance of the proposed model for aging simulations.