Balancing Interconnect Resistance and Capacitance at the Advanced Technology Nodes Based on Full Chip Analysis

This paper presents a technology-circuit cooptimization flow to achieve the best balance between wire resistance and capacitance in advanced technology nodes. It is shown that increasing the wire width to spacing ratio improves the circuit performance by up to 17.73%. In addition, we perform a sensitivity analysis on the resistance of interconnects within standard cells at the 7nm node where we show that a 2X hypothetical increase results in a 5.02% degradation in overall circuit performance, whereas a 0.5X hypothetical resistance improvement results in a 2.11% decrease in power.