Split-Fabric: A Novel Wafer-Scale Hardware Obfuscation Methodology using Silicon Interconnect Fabric

Global manufacturing of integrated circuits provides cost-effective access to high-end fabrication facilities. Offshoring intellectual property (IP) to untrusted foundries, however, makes fab-less design houses vulnerable to several issues, such as reverse engineering, overbuilding, counterfeiting, IP piracy, and insertion of malicious circuits. Several hardware security methodologies and techniques have been proposed in the past few decades to thwart hardware attacks and reduce hardware vulnerabilities. Split-Fabric, a novel wafer-scale hardware security methodology that utilizes the silicon interconnect fabric (Si-IF) technology is proposed in this paper. Split-Fabric is a secure, scalable, low-overhead, and heterogeneous hardware security methodology that supports a fully-untrusted threat model. Two benchmark circuits, a nine-stage ring-oscillator and an 8x8 SRAM array, are designed and fabricated in part using TSMC 65 inn and in part using GF 45 nm to evaluate the performance overhead of Split-Fabric at different levels of obfuscation. According to simulation results, Split-Fabric exhibits orders of magnitude lower obfuscation overhead as compared to the split manufacturing approach.