Transient State Signaling for Spectre/Meltdown Transient Cache Side-channel Prevention

The discovery of Meltdown and Spectre attacks and their variants showed that speculative execution offers a major attack surface for micro-architectural side channel attacks. The secret data-dependent traces in the CPU's micro-architectural state are not cleansed which can be exploited by an adversary to reveal victim's secrets. In this paper, we propose a cache control scheme that cooperates with a novel load store queue(LSQ) unit to nullify the cache side-channel exploited by Meltdown and Spectre attacks and their variants. In our proposed cache scheme, a new saturating reference counter is added to each cache line to hold the number of accesses since its arrival from the higher level of the memory hierarchy. For every squashed (uncommitted) speculative transient load, a corresponding flush request packet is sent to the downstream memory hierarchy. This ensures that any cache line brought into the cache by a transient load is always evicted soon after the corresponding mis-speculation commit A cache side-channel adversary can no longer detect the existence of a transiently loaded cache block. Our experiment on gem5 shows that by integrating the proposed design, Meltdown and Spectre variants that uses Flush+Reload attack to create the cache covert channel are completely closed.