SAR ADC for a Multimode Radar Transceiver with Offset Calibration

In this paper, we design a successive approximation register (SAR) analog-to-digital converter (ADC) suitable for multimode radar transceivers. For multimode radars, the sampling rate required by ADC varies according to the continuous wave (CW) or frequency modulated continuous wave (FMCW) used for operation. Therefore, depending on which waveform is used, the input is designed to enter two paths. For path 1, we obtained 9.23 bits of effective number of bits (ENOB), 57.35 dB of signal-to-noise distortion ratio (SNDR), and 64.62 dB of spurious free dynamic range (SFDR), and the power consumption was 0.3481 mW, resulting in a figure-of-merit (FOM) of 28.9 fJ/ Conv-Step. On path 2, we obtained an 8.97 bit of ENOB, 55.76 dB of SNDR, and 60.53 dB of SFDR, and the power consumption was 1.72 mu W, resulting in a FOM of 34.2 fJ/Conv-Step. Further, a circuit was constructed to reduce the offset of the comparator. As a result of 100 Monte Carlo simulations, the offset was reduced from -46 mV/+50 mV to -4 mV/+4 mV when the worst case was considered.