Impact of Fabrication Non-Uniformity on Silicon Photonic Networks-on-Chip

Multiprocessor systems-on-chip (MPSoCs) are rapidly scaling by integrating an increasingly large number of processing cores on a single chip. Consequently, conventional metallic interconnect in such systems imposes a higher power consumption to transmit an even smaller amount of data with higher latency amongst different cores. Optical technology, which has been successful in long distance communications, has indicated promising potentials to realize high performance communication in MPSoCs. As a result, optical network-on-chip (ONoC) is introduced to the communication infrastructure in MPSoCs to realize low power, low latency, and high bandwidth communication. The fundamental optical devices in such systems (e.g., optical filters and switches), however, are extremely sensitive to fabrication non-uniformity (a.k.a. fabrication process variations). In this context, precise analytical models with low computational complexity are required to fully understand the impact of different variations on the performance of ONoCs. Moreover, a comprehensive study on process variations helps determine power penalties required to trim/tune (e.g., thermal tuning) faulty devices in such systems, as well as developing required design techniques to compensate for process variations.