Design and Performance Evaluation of a Novel Dual Tunneling based TFET Considering Trap Charges for Reliability Improvement

Interface trap charges originate in the semiconductor while, fabricating the device, which occur due to the process, radiation stimulated impairments, leading to serious reliability issues in the device. In this work, reliability analysis of Stacked Oxide (SO) Extended-Source Double-Gate Tunnel FET (SO-ESDG-TFET) has been conducted for the first time. For this device, stacked oxide layer has been incorporated as the gate dielectric, which results in reduced leakage current at channel gate juncture. Incorporation of high-k material in gate stack leads to increment in coupling capacitance among channel and gate electrode, which increases the immunity of SO-ESDG-TFET towards interface charges. The reliability analysis has been carried out by studying the impact of both negative as well as positive interface traps on Analogue/RF parameters like electric field, input characteristics etc. Observation has been made that positive (negative) ITCs increase (decrease) the ON-state current of SO-ESDG-TFET and conventional ESDG-TFET by 67.05