A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process

Increased data-rates and multi-lane SerDes implementations impose stringent conditions for CDRs to produce low-jitter clocking that is capable of managing frequency and phase offsets. Consequently, high-speed phase interpolators (Pls) must be both low-power and compact for multi-lane requirements, but also high-resolution with respect to the clock period $(\mathrm{T}_{\text{period}})$ , with high static and dynamic phase linearity to minimize the PI jitter. Prior art in Pls is limited to 7-8b measured resolution [1]–[4], and INL of >500fs [1]–[4]. We present a 9b Pl; even with the additional bits, the proposed PI consumes low power of 0.43mW/GHz and a small area. The worst rotation spur is at least 8.1 dB lower (than [4]), and DNL/INL values of 295fs/510fs are $> 144\times$ better than prior-art. Implemented in 5nm technology at VDD $=075\mathrm{V}$ , our design leverages digital and analog techniques easily suited to FinFET operation.