A Robust Integrated Power Delivery Methodology for 3-D ICs

The inherent advantages of three-dimensional (3-D) integrated circuits (ICs) are well-aligned with the continuous demand for increased density of functionality, reduced latency, the power dissipation of communication, and heterogeneity of modern applications. Delivering power efficiently to highly heterogeneous voltage domains across the tiers of a 3-D IC is, however, a significant challenge. To address the power delivery challenge in 3-D ICs, a robust integrated power delivery methodology is proposed in this article. Recent advancements in the fabrication of high-density integrated passive components, and the area that is available in the vertical dimension of the 3-D construct, are exploited in this work to enable an efficient and robust power delivery system for 3-D ICs. In the proposed approach, one or more layers within the 3-D structure are dedicated to power conversion and regulation, namely, power layers (PLs). A design exploration stage is also provided to determine the number of PLs, distribution of resources between power and functional layers (FLs), assignment of voltage domains to PLs, and voltage levels across the power delivery system. The proposed methodology is compared to three other power delivery topologies and exhibits 1.4– $38\times $ and 1.4– $7.1\times $ improvement in, respectively, voltage drop and power efficiency. Results are normalized to the total on- and off-chip area dedicated to power conversion and regulation in each topology.