BiMDiM: Area efficient Bi-directional MRAM Digital in-Memory Computing

Spin transfer torque MRAM (STT-MRAM) based digital in-memory computing (IMC) has been recently proposed for energy efficient processing of convolutional neural network (CNN). The conventional MRAM based IMC architecture suffers from excessive storage area since a large number of intermediate sum and carry bits should be stored for the following successive additions during multiply-accumulate (MAC) operations. In this paper, we propose an area efficient bi-directional MRAM digital IMC (BiMDiM) scheme, where the size of memory cells storing the intermediate sums and carries can be efficiently reduced by repetitively using the same memory cells during MAC operations. In addition, to reduce the number of inefficient half-additions, which can process only two inputs with almost same hardware cost, the addition re-scheduling is also presented to further improve the energy and latency of BiMDiM. The proposed BiMDiM architecture has been simulated using 28nm CMOS process. When compared to the baseline architecture, the proposed BiMDiM improves area efficiency up to 53%.