FPGA-Based Architectures for Random Forest Acceleration

Random Forests (RF) are a widely used group of classification and regression algorithms, mainly implemented in software. Software approaches, however, can take a long time to train when using large datasets due to their complexity. Several hardware architectures have been proposed, implemented and discussed previously for hardware implementation of RFs. However the solutions are focused on a tradeoff of run time and memory. This paper proposes a method to decrease the classification training time by expanding on memory usage while keeping high accuracy compatible with CPU implementations. The proposed method is shown to decrease the timing required for training an RF by an average of 50× compared to a software implementation. The proposed architecture also improves the resulting accuracy compared to the previous literature methods while reducing run time.