Analysis and Discussion of Different Three-Phase dv/dt Filter Topologies and the Influences of Their Filter Parameters on Losses and EMC

In this paper two modified three-phase dv/dt filter networks are analysed. They're investigated in a fast switching SiC-MOSFET inverter system with the primary purpose of reducing the steep voltage slopes caused by the wide bandgap semiconductor devices at the output of the inverter. This should preserve the insulation system of a connected electrical load machine from partial discharges and deterioration. The necessity of damping down the voltage slopes outside of the inverter can arise from the possibility of lower switching losses and more favourable temperatures within the inverter. An additional filter of course will cause power losses depending on it's parameters. Hence, the influence of the passive filter parameters on those losses are an integral part of the analysis. In addition to the slope-damping of the inverter output voltage, the two discussed filter topologies should also challenge the conducted EMI of the system. Therefore, both of the circuits use special modifications to reduce the interference levels introduced by the fast switching inverter. Furthermore, a diode clamping of the filter output voltage to the DC-link potentials is implemented and it's impact on the dv / dt reduction, filter losses and EMI is discussed. Generally, a higher filter inductance, meaning a lower necessary capacitance, will reduce the extra filter losses at the expense of a higher filter volume as well as additional oscillations of the output voltage. The diode clamping leads to a significantly less overshoot and ringing of the resulting voltages, but to an increase of the measured losses. Finally, examining the influences of the different filter topologies, their parameters and the diode clamping on the conducted EMC behaviour, it will be shown that both of the modified topologies have the ability to reduce EMI levels in certain areas.