Low Temperature Sapphire to Silicon Flip Chip Interconnects by Copper Nanoparticle Sintering

The continuous trend to integrate more multi-functions in a package often involves, Heterogeneous Integration of multi-functional blocks in some kind of 3D stacking. The conventional flip chip for die-on-substrate technology applies solder for integration. However, solder joint integration has the disadvantages of restricting height, reflow issues and re-melting at high operating temperatures. Nanometallic particle sintering offers a potential solution for these solder related issues. Nanometallic particle sintering occurs at low temperature and does not reflow and melt at higher temperatures. Hence, it can be applied for quite precise alignment and integration technologies, such as photonic components on silicon for harsh environment applications. In order to test this concept, we use sapphire and Si wafers with different mechanical properties, which can lead to the coefficient of thermal expansion mismatch. The sapphire chip can operate at a higher temperature applied for ultraviolet photonics application. This report describes a novel approach using copper nanoparticles paste patterned through photolithographic stencil printing. The photoresist acts as the stencil mask, and a photoresist lift-off process is applied to strip the photoresist stencil. This process has the advantages of lithographic form factor and precision and provides a chip to chip interconnect with a standard height of 20 mu m.