An FPGA-Based Hierarchical Parallel Real-Time Simulation Method for Cascaded Solid-State Transformer

The cascaded H-bridge (CHB)-based solid-state transformer (SST) is a core interface device for power conversion in the distribution network. However, the complicated structures and higher switching frequencies bring significant challenges to real-time simulation and hardware-in-loop (HIL) testing. This article proposes a field-programmable gate array (FPGA)-based hierarchical parallel real-time simulation method for cascaded SST, which mainly includes highly parallel solving at the operation level, module level, and system level. A dual-port equivalent model of the cascaded SST is constructed based on the hierarchical parallel real-time simulation method. A cascaded SST containing 42 modules (630 components) can be simulated on a single FPGA with a minimum of 400 ns time-step. The information of the ports of the equivalent model and the information of the internal nodes of the cascaded SST can be obtained, which is the same as the simulation of detailed model. The real-time simulation of cascaded SST with input-series-output-parallel (ISOP) structure is carried out on a Xilinx Kintex-7 FPGA. The simulation results show that the real-time simulation waveforms are almost consistent with those in PSCAD/EMTDC software package.