5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O

Symposium on VLSI Technology (VLSI Technology)（2022）

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摘要

Heterogenous co-packaging of optical I/O with compute, memory or switch nodes will deliver significant improvements in power, bandwidth and reach in data center and high-performance computing applications. A first-ever real-ized and validated 5.12 Tbps co-packaged FPGA with optical I/O is presented. The Multi-Chip Package integrates a 14nm FPGA die with five Ayar Labs TeraPHY™ optical I/O chiplets.

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关键词

copackaged FPGA,data center,high-performance computing applications,multichip package,heterogenous copackaging,silicon photonic interconnect I-O,FPGA die,Ayar Labs TeraPHY optical I-O chiplets,size 14.0 nm,bit rate 5.12 Tbit/s,Si

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