Impact of sidewall spacer materials and gate underlap length on negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET)

•A negative capacitance double-gate tunnel field-effect transistor with spacer engineering is proposed for low power device.•In source/drain underlap region, different outer fringing field is needed to enhance electrical characteristics.•As a result, underlap length and dielectric constant are optimized for high on-state current and low ambipolar current.