An One-Cycle Load Transient Response and 0.81 mV/A Load-Regulation Time-Domain Cascaded-VCO-Controlled Buck Converter for Powering Gaming SoC

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC)(2022)

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摘要
Time-domain PWM controlled buck converter offers many advantages such as high switching frequency and compact area; however, it cannot fit the needs of gaming SoC in terms of <1 mV/A precise output load regulation and a fast load transient response to prevent under-voltage crash [1]–[5]. Fig 1 shows the issues of conventional time-domain PWM controlled buck converter for powering gaming SoC. The mismatch of the VCO gain $\mathrm{K}_{VCO}$ shown in the transfer curve inside the bottom of Fig 1 complicates the design. The $\mathrm{K}_{VCO}$ mismatch between two oscillators, VCO FB and VCO REF , leads to the mismatch between the control voltages of two VCOs, and results in an output voltage offset $\Delta \mathrm{V}_{OS}(= \mathrm{F}_{SW}/ \mathrm{K}_{vcoREF} \mathrm{F}_{SW}/ \mathrm{K}_{vcoFB})$. In prior art, the FLL [1], chopping [5], and calibration techniques are developed to mitigate the offset under different loading condition. However, the reported 6.25mV/A [1] and 18mV/A [5] load regulations are still insufficient. Furthermore, when the operating condition varies, such as a load transient event, the relocking and resettling procedure worsen the transient trajectory. The control loop bandwidth (BW) and maximum loading current must be compromised for a stable operation. [1]–[5] show that the load step is limited to below 510mA, and the load transient response is longer than $1.8 \mu \mathrm{s}$ even though the FSW is in the range of 10MHz. Besides, the low-cost surface-mount-device (SMD) inductor L s and multilayer-ceramic capacitor (MLCC) C o could be adopted as the $\mathrm{F}_{SW}$ increases. However, the parasitic components of output inductor $\mathrm{L}_{S}$ and output capacitor C o such as $\mathrm{C}_{Ls}$ and $\mathrm{L}_{Co}$ form an additional resonant loop as shown in top of Fig 1. This loop introduces unwanted switching noise coupled from $\mathrm{V}_{LX}$ to $\mathrm{V}_{O}$ path. For a conventional time-domain controller, the switching noise directly modulates VCO and makes the control loop unstable so that the BW and transient response are further limited.
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关键词
one-cycle,load-regulation,time-domain,cascaded-vco-controlled
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