Impact of Post-Deposition Anneal on ALD Al2O3/etched GaN Interface for Gate-First MOSc-HEMT

MOS High Electron Mobility Transistors (MOS-HEMTs) may suffer from VTH instability and hysteresis reducing device performances. Post-Deposition Anneal (PDA) of the Atomic-Layer Deposited (ALD) dielectric has the potential to increase MOS-HEMT performances but needs to be compatible with the actual integration (at CEA Leti: fully recessed Gate First MOS-channel HEMT process flow). In this work, the impact of different PDA temperatures on flat-band voltage (VFB) and its hysteresis (ΔVFB) for Al2O3 deposited on etched GaN substrates is investigated using MOS capacitors (MOSCAPs). Material properties are analyzed by Hard X-Ray Photoelectron Spectroscopy (HAXPES), Fourier Transform Infrared Spectroscopy (FTIR) and Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) analyses. With increasing PDA temperature up to 500°C: (i) ΔVFB decreases and is explained by the reduction of Ga-O bonds at Al2O3/GaN interface and O-H groups in Al2O3 (ii) VFB decreases and could be explained by the reduction of fluorine impurity concentration in Al2O3. For 600°C PDA, Grazing Incidence X-Ray Diffraction (GIXRD) analysis shows a small crystallized κ-Al2O3 signal on etched GaN contrary to the as-grown GaN. The onset of this crystallization could explain the degradation in breakdown field for PDA above 500°C observed on MOSCAPs after the Gate-First process flow overall thermal budget. Therefore, the optimized PDA temperature suggested for a fully recessed Gate First MOS-channel HEMT is 500°C.