Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking.

Oracle guided attacks, such as the SAT attack, and finite state machine (FSM) reconstruction-based structural attacks are two primary threats to sequential logic obfuscation of an integrated circuit (IC). Recent defense mechanisms apply hidden state transitions (HST) and logic cone modifications to a partitioned FSM to protect against both oracle-guided and structural attacks. HST triggering techniques are implemented on select state registers to induce controlled timing glitches in the FSM. However, the current implementations of HST are vulnerable to structural attack through the gate-level logic implementing the trigger. In this paper, a random walk-based security estimation metric is utilized to quantify the security of gate-level masking of the triggering topology. A novel coupling capacitance-based HST triggering topology is proposed, where the glitch is induced by manipulating the physical properties of the circuit rather than the gate-level logic. An average increase of 8.53x in the random walk-based security estimation score and an 887x increase in the geometric mean of the expected number paths to extract the key is observed for coupling capacitance based HSTs as compared to traditionally triggered HSTs. The schematic level equivalent of the proposed technique is implemented on a subset of ISCAS'89 benchmark circuits, resulting in an average overhead in area and power of 14.35% and 22.02% for all benchmark circuits and 2.23% and 1.25% for the four largest benchmark circuits, respectively, as compared to the original unobfuscated circuits.