Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation

Spin-orbit torque magnetic random access memory (SOT-MRAM) has recently gained great attention due to its various benefits on memory implementation. However, SOT-MRAM's read operation still shows large delay with large energy consumption, making it difficult to replace conventional CMOS-based memories. In this paper, a source-line shared (SLS) 2T SOT-MRAM cell structure is presented, where the bit-line capacitance is effectively reduced to benefit the speed and energy of the read operation. While achieving benefits in read operation, the area overhead of the SLS SOT-MRAM cell can be efficiently reduced by sharing the source line among 4 cells. The HSPICE circuit simulations using the 28 nm CMOS technology show that the proposed SLS 2T SOT-MRAM cell achieves the read energy improvement of 28.5% and read speed improvement of 37.8% while showing only 6.25% of area overhead.