Architecture Design of AVS3 Fractional Motion Estimation for 4K UHD Video Coding

The third generation of video coding standards (AVS3) has significantly improved video coding performance. It adopts three block division mechanisms, including Binary-Tree (BT) division, Quad-Tree (QT) division and extended Quad-Tree (EQT) division. These three block division increase the computation amount of fractional pixel motion estimation (FME), making it difficult to implement a real-time FME hardware. This paper proposes a 17-point fractional pixel parallel search algorithm and small-sized motion vector substitution(MVS) algorithm to reduce the number of CUs for FME. Combined with these two hardware friendly algorithms, we design a parallel pipeline architecture suitable for CUs with sizes from $4\times 4$ to $64\times 64$ . FME hardware module is divided into four circuits to process CUs of different sizes. Each circuit is divided into eight flow modules to ensure that the clock cycles required by each circuit are almost the same. These eight flow modules include data preparation, interpolation, search, rate-distortion optimization (RDO) and other modules to calculate fractional pixel motion vector (FMV) of CUs. MVS module uses the deduced FMVs to substitute FMV of the remaining CUs. Experimental results show that the proposed algorithms have 0.28% performance degradation in BD-Rate. The parallel pipeline architecture supports real-time encoding of $3840\times 2160$ @60fps.