Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

In this work, we have analyzed novel p-channel nanosheet-FET (NSFET) architectures, which utilize Ge channel grown heteroepitaxially on GaAs with an intermediate AlAs etch-stop/buffer layer. The lattice matched Ge/AlAs heterostructure offers significant benefits for gate all-around (GAA) CMOS devices such as: 1) defect-free interface and channel; 2) ease of fabrication owing to $\sim 10^{{5}}$ :1 etch selectivity between AlAs and Ge; 3) well-established and transferrable material growth and process; 4) superior performance and low-power dissipation; 5) no limitation of sheet thickness; and 6) higher number of vertically stacked sheets. The transition from the well-established FinFET architecture to the Ge p-NSFET will improve ${I}_{ \mathrm{\scriptscriptstyle ON}}$ by 12% to 0.11 mA/ $\mu \text{m}$ , subthreshold swing (SS) by 9% to 86 mV/dec, and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio by $\sim 5\times $ , at the N5 node. In addition, the use of InxGa $_{{1}-\text {x}}$ As strain template to sustain a tunable tensile strain in Ge through pseudomorphic growth can result in an additional 40% improvement in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and 8% in SS, at a strain of 1% for the p-NSFET. Leveraging the lattice matched Ge/AlAs growth, the 3-D stacking of a large number of NSs is possible, and a significant boost in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ( $\sim 4\times$ ) is obtained with eight layers despite of parasitics-induced self-loading. In applications requiring high drive current, increasing the number of stacked Ge NSs is the most efficient design pathway to improve circuit delay and area-delay-product (ADP). This system shows suitability for low-power and high-performance applications for dimensions down to N0.7, where ${I}_{ \mathrm{\scriptscriptstyle ON}}$ is $\sim $ 0.6 mA/ $\mu \text{m}$ and the SS is 81 mV/dec.