Design and Analysis of High-Throughput Two-Cycle Multiply-Accumulate (MAC) Architectures for Fixed-Point Arithmetic

There is always a growing demand to find out an efficient VLSI architecture of Multiply-Accumulate (MAC) unit which accounts for various high-speed operations involving digital signal processing and machine learning. This study aims to explore two major bottlenecks which limit the MAC unit's performance: (i) the partial products reduction network of the multiplier, and (ii) the architecture of the accumulator. Based on our exploration, we have implemented a two-cycle area efficient and high throughput synchronous MAC system using pipelining which is a well-known standard approach to improve the performance of sequential task by reducing the length of critical paths. The datapath of our proposed approach has adopted an ancient Vedic multiplication technique called Urdhva Tiryagbhyam Sutra, and two different addition schemes. Moreover, a distributed control-path scheme has been implemented for the pipelined structures which is found to be advantageous in terms of reducing the delay by distributing the logic to be near the pipeline stages. The proposed VLSI architectures has been implemented on FPGA, and the performance metrics (latency and throughput) of the same has been analyzed based on the simulation results and static timing analysis using standard tools.