A Time-Domain Parallel Counter for Deep Learning Macro.

This paper proposes a novel time-domain parallel counter that can handle large number of input bits with good power efficiency and fast speed. This new design turns parallel counting into time-domain accumulation by using two-value delay unit. The circuit is implemented with 63-bit input scheme and simulated using a 65nm CMOS technology with 1V power supply. The results show that the new architecture's speed and power increase linearly with the number of input bits which shows great potential in deep learning implementation where large-number accumulation is needed.