Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time.

System-on-chip (SoC) design is made in more complicated processes. One of the processes called clock tree synthesis (CTS) is important role in processing place & route (P&R) for designing digital chip considering the timing problem. This paper assesses that the proposed CTS framework constructs the clock tree for synthesizable register transfer level (RTL) Verilog code, and then reconstruct the buffer-inserted clock tree synthesized tree with the proposed shallow CTS algorithm. The output clock tree synthesized netlist by the proposed method is evaluated in term of the total delay and it's difference in the entire clock tree paths. This paper shows that the proposed framework can efficienty estimate the CTS results so that the given RTL codes is synthesizable.