A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS

This article presents a 25 nW–2.4 $\mu \text{W}$ switched-capacitor-based solar energy harvester with integrated maximum power point tracking (MPPT). The proposed dc–dc converter avoids charging and discharging of top and bottom plate parasitic capacitors by switching both the terminals of energy source as opposed to switching just one terminal. As a result, the energy lost in switching the top and bottom plate parasitic capacitors is zero joules, which helps to achieve highly efficient switched capacitor architecture for harvesting sub 1- $\mu \text{W}$ energy. The proposed dc–dc converter achieves same charge redistribution loss (CRL) as that of a cross-coupled dc-dc converter with half the required number of capacitors. The proposed harvester is implemented in 180 nm CMOS process and achieves an efficiency of 80% while delivering 1- $\mu \text{W}$ output and achieves a peak efficiency of 80.66% at 2.4- $\mu \text{W}$ output while maintaining a regulated output of 1.8 V.