An Automated Workflow for Generation of Neural Networks for Embedded FPGAs on IoT.

With the increasing popularity of artificial neural networks to solve a variety of issues for edge computing devices in the Internet of Things and the resource-intensive nature of these algorithms, there is a demand for hardware accelerators to optimize them. However, developing this type of device is usually locked behind specialized programming expertise and long design cycles. We propose an automatic generation workflow that, from a trained model, writes code for a hardware accelerator that optimizes the execution of the neural network that can be synthesizable in an FPGA. A proof of concept workflow with limited function compatibility was then created and an accelerator that is synthesizable in a small, low power FPGA is generated. It is then tested against a personal computer CPU, and significant speed up and energy efficiency gains are obtained.