An 8-b 8-GS/s Time-Interleaved SAR ADC With Foreground Offset Calibration in 28nm CMOS

This paper presents a high speed and low power TI-SAR ADC with offset calibration. Based on robust non-binary dynamic resistive DAC, comparator offset mismatch in the 2b/cycle TI-SAR ADC is well mitigated by the proposed offset calibration with small power consumption and speed degradation. A custom segmented and split CDAC is developed to reduce critical path delay and input capacitive load. With optimized switching strategy, VCM shift is minimized to ensure ADC accuracy and only two reference sources are needed. An 8-b 8GS/s prototype is designed in 28nm CMOS process, the simulated ADC ENOB and SFDR are 7.7bits and 63.4dB respectively with Nyquist input frequency. The ADC power consumption is 14.3mW under 1-V supply, corresponding to an excellent Walden FoM of 8.5 fJ/conv.-step.