A Third-Order CIFF Noise-Shaping SAR ADC with Nonbinary Split-Capacitor DAC

A third-order CIFF noise-shaping SAR ADC is proposed in this paper. Aiming at the input-referred noise of the multi-input comparator, stacking capacitors are used to realize the addition of the input signal and integrated residual voltages. To reduce area and power consumption, a nonbinary spilt-capacitor DAC is proposed. The DAC input capacitor is 0.6pF. A sampling rate of 5MS/s ADC is designed in 130nm process. The simulation results show that with the oversampling ratio of 8, the ADC achieves 80.2dB SNDR and 86.8dB SFDR, and the ENOB is 13bits. The total power consumption of the ADC is about 607μW.