Gate electrostatic controllability enhancement in nanotube gate all around field effect transistor (vol 13, 065006, 2023)

Recently, short channel effects (SCE) and power consumption dissipation problems pose big challenges which need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters into sub-10nm technology node. From 3nm technology node and beyond, gate all around field effect transistor steps onto the history stage attributed to its improved SCE suppressing ability thanks to surrounding gate structure. Herein, we demonstrate the super electrostatic control ability of a double-gated nanotube gate all around field effect transistor (DG NT GAAFET) in comparison with nanotube (NT GAAFET) and nanowire gate all around field effect transistor (NW GAAFET) with the same device parameters designed. Ion boosts of 62% and 57% have been obtained in DG NT GAAFET in comparison with those of NT GAAFET and NW GAAFET. Besides, substantially suppressed SCEs have been obtained in DG NT GAAFET due to enhanced electrostatic control, which are certificated by improved Ioff, SS, and Ion/Ioff ratio obtained. On the other hand, the Ion of NT GAAFET is comparable with that of NW GAA-FET. Whereas, its Ioff is 1 order smaller, and SS is almost 2 times smaller compared with those of NW GAA-FET, manifesting the meliority of nanotube channel structure. In the end, the robustness of nanotube channel structure, especially double gated one, against Lg scaling has been verified with TCAD simulation study.