A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < −80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging

This paper presents an approach to the mitigation of harmonic distortions in wideband current-steering digital-to-analog converters (DACs). This approach enables code-independent constant-switching-activity data-weighted-averaging (CSA-DWA) with the extra area and power overhead by exploiting redundant current sources. With CSA-DWA, a 16-bit 4.0-GS/s calibration-free DAC is designed in 65 nm CMOS. To achieve high-speed low-complexity CSA-DWA decoding, the most-significant-bit (MSB) segment is set to 5 bits. The MSB switching activities are regulated to be constant with 1-bit randomized switching activity to minimize the non-linearity due to the MSB switching activity truncation errors in the CSA-DWA decoder. Furthermore, a power delivery scheme is adopted to reduce the IR-drop mismatch between the switching elements. Experimental results show that this DAC achieves $>$ 70 dBc spurious-free dynamic range (SFDR) and $< -80$ dBc third-order intermodulation distortion (IM3) up to 1 GHz. With the proposed CSA-DWA, SFDR and IM3 are improved by 4–15 dB and 5–14 dB, respectively, across the Nyquist band.