Harnessing Fault Tolerant Capabilities of USE Clocking Scheme for Designing QCA Flip- flops

Quantum-dot cellular automata (QCA) proves tself to be a promising nano-scale technology for development of integrated circuits and systems. QCA technology requires clocking to power and synchronize the logic. Among the several clocking mechanisms available in QCA, the Universal, Scalable md Efficient (USE) clocking scheme has some inherent advantages of better realizability and fault tolerance. This paper proposes QCA layouts for D, RS, JK, and T flip- flops using USE clocking scheme. The impact of using USE clocking scheme on fault tolerance of the flip flops is analyzed against single cell omission defect. The QCA layouts of flip flops exhibits 47.83%, 48.275, 35.29%, and 41.55% fault tolerance or D, RS, JK and T flip flops respectively.