A Fully Integrated 0–200-MHz System BW Wireless Direct Sampling Receiver in 14-nm FinFET

IEEE Solid-State Circuits Letters(2023)

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摘要
This letter presents a fully integrated wireless direct sampling receiver (DSR) that covers from dc to 200-MHz system bandwidth implemented with a single-channel SAR ADC in 14-nm FinFET. To demonstrate the proposed architecture, frequency modulation (FM) among the applicable standard frequency bands is adopted as a prototype. The measured demodulated SNR is 73.9 dB with −47-dBm input power at 108 MHz and the sensitivity level is −106 dBm. The proposed DSR shows a robust performance over a 30-dB-demodulated SNR even in the presence of the interference, such as a strong adjacent channel and an in-band spur. Furthermore, the FM channel scan time is drastically reduced since the proposed receiver simultaneously samples all channels without adjusting analog building blocks.
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关键词
Direct sampling receiver (DSR),frequency modulation (FM),phase-locked loop (PLL),successive-approximation register (SAR) analog-to-digital converter (ADC)
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