iMCU: A 102-μJ, 61-ms Digital In-Memory Computingbased Microcontroller Unit for Edge TinyML

2023 IEEE Custom Integrated Circuits Conference (CICC)(2023)

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TinyML envisions performing a deep neural network (DNN)-based inference on an edge device, which makes it paramount to create a neural microcontroller unit (MCU). Toward this vision, some of the recent MCUs integrated in-memory computing (IMC) based accelerators [1–3]. However, they employ analog-mixed-signal (AMS) versions, exhibiting limited robustness over process, voltage, and temperature (PVT) variations [1–2]. They also employ a large amount of IMC hardware, which increases silicon area and cost. Also, they do not support a practical software dev framework [1–3] such as TensorFlow Lite for Microcontrollers (TFLite-micro) [5]. Because of this, those MCUs did not present the performance for the standard benchmark MLPerf-Tiny [6], which makes it difficult to evaluate them against the state-of-the-art neural MCUs. In this paper, we present $i M C U$, the IMC-based MCU in $28 \mathrm{~nm}$, which outperforms the current best neural MCU (SiLab’s xG24-DK2601B [6]) by 88X in energy-delay product (EDP) while performing MLPerfTiny. Also, iMCU integrates a digital version of IMC hardware for maximal robustness. We also optimize the acceleration targets and the computation flow to employ the least amount of IMC hardware yet still enable significant acceleration. Hence, iMCU’s total area is only $2.03 \mathrm{~mm}^{2}$ while integrating $433 \mathrm{~KB}$ SRAM and $32 \mathrm{~KB}$ IMC SRAM.
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