DSEAdd: FPGA based Design Space Exploration for Approximate Adders with Variable Bit-precision

Functional approximation methods have been used to exploit the inherent error tolerance of several applications. Approximate computing reduces the resources utilized at the cost of acceptable accuracy loss. Designers need to follow a systematic approach to arrive at an optimized design configuration based on certain constraints. In this work, we present DSEAdd: an FPGA-based automated design space exploration (DSE) framework targeting variable bit-width approximate adders. Given a certain area, timing or accuracy (ATA) constraint, the approach helps to identify the best adder configuration. We introduce a metric known as Figure of Merit (FOM) to quantify the area, performance and accuracy of the design. We test the DSE framework by running a set of 74 design configurations. We demonstrate the use of FOM as a metric to choose the best adder configuration. We observe that we can obtain an area-optimized design with a 9.7% reduction in resource usage at the cost of only 0.3% accuracy, but with a lower bit precision (8-bit instead of 32-bits). Further, at low bit precisions, a slight compromise in the area (0.35%) can help improve the accuracy dramatically (17.7%). To achieve the best trade-off between accuracy and resources, we propose a configuration with 2 or 3 sub-adders. Lastly, we note that a performance-optimized design is difficult to achieve at higher bit-precision.