A CMOS Buffer Amplifier with Slew-Rate Enhancement and Power Saving Techniques

This paper presents a low-power buffer amplifier with a high slew rate. The buffer amplifier with cross-coupled input pairs and positive feedback enhances the driving current at the transients dynamically. The adaptive bias-switching scheme reduces static power consumption. The design was fabricated in a 0.18-mu m CMOS process. The proposed amplifier offers a slew rate of 13.42 V/mu s at a load capacitor of 100 pF with a static current of 2.38 mu A, which is 80 times better than the one without the current-boosting scheme. The chip area is 189 x 144 mu m(2).