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Low Dit of $(2-4)\times 10^{10}$ using Y2O3/epi-Si/Ge Gate Stacks

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)(2023)

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摘要
In this work, we have achieved record-low interfacial trap densities of $(2-4) \times 10^{10}$ eV −1 cm −2 in the Y 2 O 3 /epi-Si/Ge(001) gate stacks, particularly low $D_{it}$ less than $1 \times 10^{11}$ eV −1 cm −2 near the conduction band region. Synchrotron radiation photoemission was used to probe the interfacial bonding with atomic hydrogen exposure to elucidate the effect of post-metallization annealing in forming gas. After exposure of atomic hydrogen at 400°C, a great reduction of GeO x and a great increase of SiO x formation, which is stabilized in Si 3+ states, suggest that the Y-O-Si formation attributed to the low $D_{it}$ .
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