Common Source Inductance Compensation Technique for Dynamic Current Balancing in SiC MOSFETs Parallel Operations

In high-current applications such as traction inverters, SiC MOSFETs are paralleled to increase the current rating. One major issue with paralleling SiC MOSFETs is the dynamic current imbalance. The unbalanced dynamic current could lead to severe device and system failures. A well-known root cause of dynamic current imbalance is the parasitic inductance imbalance due to asymmetrical layout. In this article, a common source inductance (CSI) compensation technique is proposed for SiC MOSFETs in parallel operations to reduce the dynamic current imbalance due to layout asymmetry. With the proposed technique, the dynamic current among paralleled switches is evenly distributed even when the layout is not symmetrical. The improved current sharing is achieved by designing the common source inductance of each paralleled device inversely proportional to its power loop inductance. Because of the balanced dynamic current, the reliability of the circuit with the proposed layout can be significantly improved. In addition, the proposed CSI compensation technique could help reduce the peak current in case of a short circuit, hence improving module reliability. The proposed technique is an easy-to-implement design that requires no additional components. A half-bridge configuration with SiC discrete devices in parallel and a multichip power module with SiC dies in parallel are built to verify the effectiveness of the proposed technique. The proposed technique could improve the current sharing in both prototypes.