Complex Dynamic Analysis, Circuit Design and Simplified Predefined Time Synchronization for a Jerk Absolute Memristor Chaotic System

In this parper, a 4D absolute memristor Jerk chaotic system is proposed. Firstly, complex dynamics are studied by phase diagram, Poincare section, power spectrum, bifurcation diagram, 0-1 test, and Lyapunov exponent spectrum. Then, the period doubling bifurcation, degradation, and offset boosting are revealed. For the feasibility of practical application, the analog circuit and FPGA digital circuit are designed. Finally, a simplified predefined time synchronization scheme is proposed; comparing with the full control input synchronization scheme, the simplified predefined time synchronization scheme can not only reduce the controller inputs but also predefine the synchronization time.