A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT.

With only an input-swing-comparable supply voltage, the ADC input buffer gives rise to a significant static distortion, inevitably calling for a large supply headroom for adequate linearity [1] [2]. A negative supply voltage is often necessary to maintain a proper input common mode voltage for the backend ADC that burdens the power management unit and induces reliability concerns. As an alternative, digital calibrations [3] [4] [5] are utilized to tackle the buffer’s impairments. While calibrating the dynamic distortion renders an excessive power/area cost with a constrained input [3] [4], the static distortion calibration is more reasonable. In [5], an auxiliary ADC is introduced as a reference for calibration, omitting the negative supply and showing a Nyquist SFDR of $\sim$67dB in a 12b1GS/s ADC. However, the auxiliary ADC must reach adequate linearity, which is bulky and complex. The digital processing for correction is also costly [6]. This paper proposes a background input buffer calibration with a mild analog circuit overhead and the correction is on-chip in the analog domain, achieving < 76dB SFDR at Nyquist input.