Jitter Compensation Mechanism for Dynamic Deterministic Networks.

Guillaume Soudais,Tarik Graba,Yves Mathieu,Sébastien Bigo

OFC（2023）

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摘要

We compensate jitter between any two unsynchronized endpoints by tracking their clocks and re-creating flows by retiming packets. After implementation over FPGA, we achieve similar to 10ms synchronization setup time with no more than 70ns jitter. (c) 2023 The Authors

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关键词

clocks,compensation mechanism,dynamic deterministic networks,time 10.0 ms,time 70.0 ns,unsynchronized endpoints,~10ms synchronization setup time

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